Comparator-based Analog-to-Digital Converter (ADC) has always been a very popular research topic, such as ADCs having various architectures like Flash, Folding, Successive Approximation Register (SAR) and Sub-Ranging, etc. Since a Comparator-based ADC has characteristics of high speed, high resolution, low power consumption, and small area which will be more apparent with the progress in advanced semiconductor manufacturing techniques, such ADCs are indeed suitable for system integration. In addition, in cooperation with a self-timed timing control mechanism, the circuit complexity of the clock signal generator within the ADC is simplified, and a sampling rate of the ADC is increased. Therefore, self-timed comparator-based ADC has gradually become one of the technical focuses that researchers compete in developing.
However, when a self-timed comparator compares input signals while the input difference of the input signals is close to zero, the self-timed comparator is not able to successfully generate a comparison result within a required time interval. Thereby, the self-timed comparator enters a Metastable State. When the self-timed comparator enters the Metastable State, generation of a next self-timed signal is seriously delayed, which thereby affects the timing in the operation of the system and enhances the Bit Error Rate (BER) of the system. Therefore, how to reduce the probability of the self-time comparator entering the Metastable State is the major key to whether a self-timed system is able to run normally for a long time.